Complementary metal oxide silicon (CMOS) driven at low voltages and logic element devices driven at high voltages can be combined on a single semiconductor substrate. When driven at a high voltage, these devices may have high breakdown voltages for the operation at the high voltage. In order to obtain the high breakdown voltage, a density of an impurity doped into a well formed in the semiconductor substrate is typically decreased.
Referring to FIGS. 1A and 1B, a plan view illustrating a structure of a conventional high voltage transistor and a cross section illustrating the high voltage transistor taken along a line 1B-1B′ of FIG. 1A will be discussed. The cutaway line 1B-1B′ is drawn partially along an active region 30 and a device isolation film 20 for convenience of description. As illustrated in FIGS. 1A and 1B, a first well 12 doped with an impurity of a first conductivity type, for example, a p-type, is formed in a semiconductor substrate 10. A device isolation film 20 forming a field region defines an active region 30. A gate electrode 42 is formed on the semiconductor substrate 10 by interposing a gate insulating film 40 in a central portion of the active region 30. Furthermore, second wells 14 doped with an impurity of the second conductivity type, for example, an n-type, opposite to the first conductivity type are disposed in both sides of the gate electrode 42. The second well 14 is diffused partially to lower portions of the device isolation film 20 and the gate electrode 42.
A source/drain region 16 separated from the gate electrode 42 by a predetermined distance is formed within the second well 14, and a silicide layer 18 may be formed on the source/drain region 16 for improving conductivity. The source/drain region 16 is doped with an impurity of the second conductivity at a high density. The doping density of the second well 14 is relatively higher than that of the first well 12 but relatively lower than that of the source/drain region 16.
Meanwhile, the high voltage transistor uses a driving voltage of 30 volts or higher for its distinctive property. The high driving voltage causes a change in a profile of the doping density of the first well 12 having the relatively low doping density. Moreover, segregation of the impurity within the first well 12 occurs when performing a succeeding heat treatment. For example, in case of an NMOS transistor, the segregation of boron (B) of the first conductivity type occurs in succeeding heat treatment, so that a density of the boron is decreased at an edge of the device isolation film 20.
The segregation may result in a weak inversion at a portion a of the second well 14 intruding to the lower portion of the device isolation film 20 or a portion b of the device isolation film 20 contacting the active region 30. In other words, the segregation of the impurity causes the weak inversion, which then forms a parasitic MOS transistor in the portion a intruding to the lower portion of the device isolation film 20 out of the lower portion of the device isolation film 20 or the portion b of the device isolation film 20 contacting the active region 30.
Referring now to FIG. 2, a graph plotting a relation of a drain current Id versus a gate voltage Vg in order to check an influence of a parasitic transistor with respect to the conventional high voltage transistor will be discussed. It was measured that a back bias voltage Vb was varied from 0.0V to −3.0V. Furthermore, wafers used for the experiment were selected by random sampling, in which a wafer corresponding to thick solid lines was denoted by A, and a wafer corresponding to thin solid lines was denoted by B. Portions involving humps were emphasized by a rectangle c.
As illustrated, an off current Ioff of the wafer A was roughly 0.08 pA/μm, a threshold voltage Vth was roughly 1.08V, and a saturated drain current Id(sat) was roughly 344 μA/μm, so that relatively slight hump was occurred. However, an off current Ioff of the wafer B was roughly 97.12 pA/μm, a threshold voltage Vth was roughly 1.09V and a saturated drain current Id(sat) was roughly 346 μA/μm, so that the hump greater than that of the wafer A was produced. Since the wafers were selected by the random sampling, a relatively great hump may be occurred in a certain wafer. The hump caused by the parasitic transistor possibly produces a great leakage current. The parasitic transistor may result in a sub-threshold leakage current in some excessive cases.